ZX Spectrum +3 RAM and ROM Memory Mapping Explained

This article provides a technical overview of how the Sinclair ZX Spectrum +3 manages its memory architecture, specifically focusing on the interaction between its 128KB of RAM and 64KB of ROM within the Z80 CPU’s 64KB address space. It details the bank switching mechanism controlled by specific I/O ports, explains the logical division of memory pages, and describes how the system switches between the BASIC interpreter and the +3 DOS without exceeding the processor’s addressing limits.

The Z80 Address Space Limitation

The foundation of the ZX Spectrum +3 memory management system lies in the limitations of its Z80B CPU. The Z80 processor utilizes a 16-bit address bus, which inherently limits the directly addressable memory space to 64KB. However, the physical hardware of the +3 contains significantly more memory than this limit allows, featuring 128KB of random access memory (RAM) and 64KB of read-only memory (ROM). To utilize this extra physical memory, the engineers implemented a memory mapping system that allows different sections of physical RAM and ROM to be swapped into the CPU’s visible address space dynamically.

Physical Memory Configuration

The physical memory is organized into specific banks to facilitate this swapping. The 128KB of RAM is divided into eight banks of 16KB each. Similarly, the 64KB of ROM is divided into four banks of 16KB. These ROM banks include the standard Sinclair BASIC interpreter, the +3 Disk Operating System (DOS), and other utility routines. Since the CPU can only see 64KB at any one time, the system divides this visible space into four pages of 16KB each. Pages 1 and 2, covering the address range from 0x4000 to 0xBFFF, are typically always mapped to RAM banks. Pages 0 and 3, covering the lower and upper 16KB of the address space, are the primary areas used for bank switching.

The Paging Mechanism

Memory mapping on the +3 is controlled by the Uncommitted Logic Array (ULA) or ASIC, which acts as a memory management unit. This hardware listens for writes to specific I/O ports to change the memory configuration. The primary port used for RAM paging is 0x7FFD. Writing to this port allows the software to select which 16KB RAM bank appears in the upper memory page (0xC000 to 0xFFFF). This design ensures that the stack and display file, which usually reside in the upper memory, can be moved or duplicated, allowing for features like shadow screens or smooth scrolling without CPU contention on the visible memory.

ROM Bank Selection and DOS Integration

A key differentiator for the +3 compared to earlier 128K models is the handling of the ROM space. The lower memory page (0x0000 to 0x3FFF) can be mapped to either RAM bank 0 or one of the ROM banks. Selection between the different ROM banks, such as switching from the BASIC interpreter to the +3 DOS, is managed via port 0x1FFD. By writing specific values to this port, the system asserts control lines that select the appropriate 16KB ROM chip bank. This allows the computer to boot into BASIC for standard programming or switch context to the DOS for disk operations, effectively extending the functionality of the machine without requiring additional hardware ports for memory expansion.

Conclusion

The Sinclair ZX Spectrum +3 successfully overcame the 64KB addressing barrier of the Z80 CPU through a sophisticated bank switching architecture. By using I/O ports to control an ASIC that maps physical memory banks into logical address pages, the system provided access to 128KB of RAM and multiple ROM contexts. This memory mapping strategy was crucial for the +3’s ability to run a disk operating system alongside standard BASIC programs, representing a significant evolution in the Sinclair hardware design philosophy.