ZX Spectrum+2 Screen Memory Mapping Explained

The Sinclair ZX Spectrum+2 utilized a unique memory architecture to render graphics, relying on a specific interleaved mapping scheme managed by the Uncommitted Logic Array (ULA). This article explores how the system allocated RAM for video data, the non-linear arrangement of screen bytes, and the relationship between the Z80 processor and display hardware. Understanding this structure is essential for developers working with retro hardware or emulators seeking accuracy.

The Basic Memory Layout

The ZX Spectrum+2, like its predecessors, was built around the Z80 CPU and a custom ULA chip. The system typically operated with 48KB of RAM accessible in the default mode, though the +2 hardware was based on the 128K architecture. For screen display purposes, the memory map remained consistent with the original 48K Spectrum. The video memory began at decimal address 16384 (hexadecimal 0x4000) and occupied 6912 bytes of contiguous RAM. This region was distinct from the area used for program code and variables, which usually started above the screen memory at address 23296.

Interleaved Screen Structure

Unlike modern systems where screen memory is often linear, the Spectrum used an interleaved mapping strategy to simplify the hardware design of the ULA. The screen was divided into three main vertical sections, each containing 8 character rows. Within the memory map, these sections were not stored sequentially. Instead, the first third of the screen occupied the first 256 bytes of each character row block, followed by the second third, and then the final third.

Each character cell consisted of 8x8 pixels. In memory, the 8 bytes representing the pixel lines of a single character cell were stored contiguously. However, moving from one character row to the next required jumping across memory blocks rather than simply incrementing the address. This non-linear arrangement meant that drawing a vertical line was computationally more expensive than drawing a horizontal one, as the CPU had to calculate significant address offsets to move down the screen.

Attribute Memory and Color

Following the 6144 bytes of pixel data, the final 768 bytes of the screen memory region were dedicated to attribute data. Each byte in this section corresponded to a single 8x8 character block on the display. These attribute bytes defined the color scheme for that block, containing bits for ink color, paper color, brightness, and flashing effects. Because attributes were tied to character blocks rather than individual pixels, this architecture resulted in the characteristic color clash associated with Spectrum graphics, where two different colored objects overlapping in the same 8x8 cell would interfere with each other’s color data.

The Role of the ULA and Contention

The Uncommitted Logic Array was responsible for reading the screen memory and generating the video signal without direct CPU intervention. The ULA accessed the RAM during specific clock cycles to fetch pixel data for the television beam. This created a phenomenon known as memory contention. When the ULA was accessing memory to refresh the display, the Z80 CPU was sometimes forced to wait, effectively slowing down processing speed during screen drawing operations. This contention was most severe within the screen memory region, influencing how programmers optimized their code for speed versus visual fidelity.

Conclusion

The memory mapping of the Sinclair ZX Spectrum+2 was a clever engineering compromise that minimized hardware costs while delivering a functional graphical display. By using an interleaved screen structure and dedicated attribute memory, the system managed to render color graphics within strict memory constraints. Although this approach introduced complexities for software developers regarding address calculation and color clash, it remains a defining characteristic of the platform’s legacy in computing history.