Sinclair ZX Spectrum+ Video Memory Mapping Guide

The Sinclair ZX Spectrum+ utilized a specific memory mapping strategy to render graphics, relying on a dedicated section of RAM managed by the Uncommitted Logic Array (ULA). This article explores how the system allocated memory for the display, detailing the starting address, the division between pixel and attribute data, and the unique screen layout designed to optimize hardware performance. Understanding this architecture explains both the machine’s graphical capabilities and its notorious colour clash limitations.

Hardware Context and the ULA

The ZX Spectrum+ retained the 48KB RAM architecture of the original 1982 Spectrum, driven by a Z80A processor running at 3.5 MHz. The critical component for display management was the ULA, which handled video output, memory refresh, and I/O without requiring dedicated video RAM. Instead, the system used a portion of the main system RAM to store screen data. This design choice kept manufacturing costs low but imposed strict constraints on how memory was accessed and organized during the video refresh cycle.

Screen Memory Address Range

In the ZX Spectrum+ memory map, the screen display data occupies a contiguous 6912 bytes of RAM. This block begins at decimal address 16384, which corresponds to hexadecimal address 0x4000. The memory range extends from 16384 to 23295. Within this block, the first 6144 bytes are dedicated to pixel data, defining the monochrome bitmap structure, while the remaining 768 bytes store colour and attribute information. The CPU could write directly to this memory range to update the screen, allowing for fast graphics manipulation without complex video hardware registers.

Non-Linear Display Layout

Unlike modern systems where screen memory is typically linear, the Spectrum+ used a segmented memory layout to accommodate the dynamic RAM chips used in its construction. The 256x192 pixel screen was divided into three horizontal thirds. The top third of the screen occupied the first 2048 bytes of screen memory, the middle third occupied the next 2048 bytes, and the bottom third occupied the final 2048 bytes of pixel data. Within each third, the screen was further divided into character rows of 8 pixels high. This organization allowed the ULA to refresh the DRAM rows efficiently while generating the video signal, but it required programmers to calculate addresses carefully rather than using simple linear offsets.

Attribute Bytes and Colour System

Following the pixel data, the 768-byte attribute file defined the colour for each 8x8 pixel character block on the screen. Each attribute byte controlled a single block and contained specific bits for foreground ink, background paper, brightness, and flash effects. The system supported 15 colours, split into normal and bright variants. Because colour information was stored per 8x8 block rather than per pixel, any pixel within that block shared the same ink and paper settings. This memory mapping decision is the primary cause of the “colour clash” phenomenon, where moving multicoloured sprites across a background would often inherit incorrect colours within their assigned character blocks.

Impact on Software Development

The specific memory mapping of the ZX Spectrum+ dictated how developers wrote games and applications. To achieve smooth scrolling or animation, programmers often had to write optimized machine code that respected the non-linear address structure. Some software utilized alternative screen memory locations for double buffering, copying the finished frame to the visible 16384 address during the vertical blanking interval to prevent tearing. While the memory mapping imposed limitations compared to contemporaries with dedicated video chips, its direct accessibility allowed for rapid screen updates that defined the era of home computing graphics.