How ZX Spectrum+3 Managed CPU and ULA Memory Contention

This article explores the technical mechanisms behind the Sinclair ZX Spectrum+3 memory architecture, specifically focusing on how the system resolved conflicts between the processor and video hardware. It details the role of the Uncommitted Logic Array (ULA) in prioritizing video data access and explains the CPU halt states that occur during screen refresh cycles to prevent data corruption.

The Sinclair ZX Spectrum+3, like its predecessors, utilized a shared memory architecture where both the Z80 CPU and the Uncommitted Logic Array (ULA) required access to the same dynamic RAM (DRAM). The ULA was responsible for generating the video signal, which required constant reading of pixel data from memory to refresh the television screen. Since the DRAM could not service both the CPU and the ULA simultaneously, a method of arbitration was necessary to manage memory contention without causing visual artifacts or system crashes.

To manage this contention, the ULA was designed with higher priority than the CPU regarding memory access. During the periods when the video beam was active and required pixel data, the ULA would assert a WAIT signal on the Z80 processor. This forced the CPU to pause its operations for specific clock cycles, effectively halting it while the ULA fetched the necessary video information. This process occurred repeatedly during each horizontal scan line, specifically during the visible display area and parts of the border where pixel data was still being fetched.

The timing of these halt states was synchronized with the television broadcast standard, typically PAL or NTSC depending on the region. On a standard PAL machine, the CPU nominally ran at 3.54 MHz, but due to these contention wait states, the effective processing speed was reduced during video generation. The contention pattern was consistent, occurring in blocks of clock cycles that aligned with the memory access requirements of the video circuitry. This ensured that the video output remained stable and free from snow or tearing, even while the CPU was executing code.

While this memory contention strategy ensured video stability, it had implications for software performance. Developers had to account for the variable speed of the CPU, as code execution times would differ depending on whether the instructions were fetched during a contention window or a free window. The ZX Spectrum+3 maintained this legacy architecture from the 128K model, ensuring compatibility with existing software while integrating the new disk interface. Ultimately, the prioritization of the ULA over the CPU was the key mechanism that allowed the hardware to manage memory contention effectively.