How WonderSwan Color Handles Interrupts During Game Execution

This article provides a technical overview of the interrupt request system within the Bandai WonderSwan Color handheld console. It examines the role of the NEC V30 MZ CPU, identifies the primary interrupt sources available to developers, and explains the step-by-step process of how hardware signals pause game execution to run specific service routines before returning control to the main loop.

The NEC V30 MZ CPU Architecture

At the heart of the WonderSwan Color lies the NEC V30 MZ microprocessor, an x86-compatible CPU running at approximately 3.072 MHz in Color mode. Like standard x86 architectures, this processor manages interrupts through a dedicated vector table and specific flag registers. The CPU is designed to suspend its current instruction stream temporarily when an interrupt request (IRQ) is received, provided that interrupts are globally enabled via the Interrupt Flag (IF) in the flags register. This architecture allows the system to respond to time-critical hardware events without requiring the main game loop to constantly poll hardware states.

Primary Interrupt Sources

Several hardware components can trigger interrupt requests during game execution, each serving a distinct purpose for system stability and gameplay logic. The most critical interrupt for game developers is the Vertical Blank (VBLANK) interrupt, which occurs when the screen finishes drawing a frame. This signal is essential for updating game logic and video memory without causing screen tearing. Other sources include the Horizontal Blank (HBLANK) interrupt for fine-grained graphical effects, timer interrupts for precise timing operations, and serial interrupts for multiplayer communication via the link cable. Each source is assigned a specific vector number that points to the memory address of the corresponding Interrupt Service Routine (ISR).

The Interrupt Handling Process

When a hardware component asserts an interrupt request, the CPU completes the current instruction and checks the status of the Interrupt Flag. If interrupts are enabled, the processor pushes the current flag state, code segment, and instruction pointer onto the stack to preserve the execution context. It then clears the Interrupt Flag to prevent nested interrupts unless specifically re-enabled within the routine. The CPU uses the interrupt vector number to locate the address of the ISR in the interrupt vector table stored in low memory. Execution jumps to this address, where the developer’s code handles the specific hardware event, such as copying sprite data to video RAM during VBLANK.

Register Control and Masking

Developers manage interrupt behavior through specific memory-mapped registers, primarily the Interrupt Enable Register and the Interrupt Flag Register. These registers allow software to mask specific interrupt sources, ensuring that only high-priority events trigger a context switch. For example, a game might disable HBLANK interrupts during intensive graphical updates to conserve CPU cycles while keeping VBLANK interrupts active to maintain frame synchronization. Once the ISR completes its tasks, it executes an IRET (Interrupt Return) instruction. This command pops the saved state from the stack, restores the Interrupt Flag, and resumes the main game execution exactly where it left off.

Implementation in Game Development

Effective interrupt handling is crucial for maintaining performance on the WonderSwan Color due to its limited processing power. Best practices dictate that ISRs should be as short as possible to minimize latency in the main game loop. Heavy calculations are typically avoided inside the interrupt routine; instead, the ISR sets a flag or copies minimal data, signaling the main loop to process complex logic during the next frame. By synchronizing game updates with the VBLANK interrupt, developers ensure smooth animation and responsive controls while preventing visual artifacts caused by writing to video memory during the active display period.