How VIC-20 Managed Video Memory Access During CPU Cycles

The Commodore VIC-20 utilized a shared memory architecture where the Video Interface Chip and the CPU competed for bus access, necessitating a strict priority system. This article explains the cycle stealing mechanism employed by the VIC chip, which halted the processor during video fetch periods to ensure stable display output. We will examine the technical implications of this bus arbitration on system performance and memory mapping.

The core of the VIC-20’s video handling lay in its custom MOS 6560 or 6561 Video Interface Chip, depending on the region. Unlike modern systems with dedicated video RAM, the VIC-20 stored screen data in the same main memory pool used by the 6502 microprocessor. This design saved costs but created a bottleneck, as both chips required access to the system bus to read and write data simultaneously.

To resolve this conflict, the VIC chip implemented a cycle stealing protocol. The 6502 CPU typically accesses memory during one phase of the clock cycle, while the VIC chip utilized the alternate phase. However, during active video generation, the VIC required more bandwidth than the idle phases could provide. Consequently, the VIC chip would assert control over the address and data buses, effectively halting the CPU whenever it needed to fetch character codes, color attributes, or sprite data.

This arbitration meant the CPU was only free to execute instructions during the vertical blanking interval or when the VIC was not actively drawing the raster line. During the visible screen area, the processor was frequently paused, reducing its effective speed from the nominal 1.023 MHz to approximately 0.88 MHz. This management strategy ensured glitch-free video output but required programmers to account for reduced processing power during screen updates.

The memory map was structured to accommodate this access pattern, with specific blocks of RAM allocated for video data that the VIC could reach without interference. By prioritizing video memory access during critical display cycles, the VIC-20 maintained a stable television signal while allowing the CPU to operate during the remaining available cycles.