How the Sinclair ZX81 Managed Memory Mapping Between ROM and RAM

The Sinclair ZX81 utilized a distinct memory mapping architecture managed by its custom Uncommitted Logic Array (ULA) to optimize its limited 64KB address space. By strategically positioning the 1KB ROM at the top of the memory map and allocating RAM to the lower-middle section, the system enabled the Z80 CPU to efficiently access BASIC instructions and user data. This article examines the specific address allocation, the role of the ULA in handling bus contention, and the technical methods used to switch between processing and video generation without dedicated video memory.

The foundation of the ZX81 memory system lies in the Z80A CPU, which supports a 64KB addressable memory space ranging from 0x0000 to 0xFFFF. Unlike modern computers with complex memory management units, the ZX81 relied on simple decoding logic to assign specific regions of this space to physical hardware. The 1KB ROM, containing the Sinclair BASIC interpreter and machine code routines, was mapped to the very top of the address space from 0xF800 to 0xFFFF. This placement ensured that the reset vector and essential system calls were always available at predictable high-memory addresses immediately upon startup.

RAM allocation was designed to maximize the utility of the available address space while accommodating the video generation process. The internal 1KB RAM, expandable to 16KB via an external pack, was mapped starting at address 0x4000. This left large gaps in the memory map between 0x0000 and 0x3FFF, as well as between 0x8000 and 0xF7FF, which were generally unused. By placing RAM at 0x4000, the system ensured that the display file, system variables, and user program storage resided in a contiguous block that the ULA could access sequentially during the television raster scan.

The custom ULA chip was the critical component responsible for managing the interaction between the CPU, ROM, and RAM. It handled the chip select signals that enabled either the ROM or RAM based on the address lines provided by the Z80. Furthermore, the ULA managed bus contention, a necessity because the ZX81 lacked dedicated video RAM. To generate the video signal, the ULA had to read memory contents directly to determine pixel data for the screen. When the CPU needed to access memory simultaneously, the ULA would halt the processor using the WAIT signal, effectively time-slicing access to the RAM.

This memory access strategy resulted in the famous “slow” and “fast” modes of the ZX81. In slow mode, the ULA prioritized video generation, halting the CPU during the visible screen draw period to read the display file from RAM. This ensured a stable picture but significantly reduced processing speed. In fast mode, the video generation was disabled, allowing the CPU unrestricted access to memory for calculations, which was useful for running complex programs without screen output. This dynamic management of memory access allowed the ZX81 to function as both a computing device and a video generator using a single pool of RAM.

Ultimately, the memory mapping of the Sinclair ZX81 was a testament to cost-effective engineering constraints. By fixing the ROM at the top of the address space and placing RAM in a dedicated lower segment, the design simplified the decoding logic required on the motherboard. The reliance on the ULA to mediate access between the CPU and memory components allowed Sinclair to produce an affordable home computer that maximized the utility of every kilobyte available within the Z80’s addressing capabilities.