How the Sinclair ZX Spectrum+ Managed Screen Memory

The Sinclair ZX Spectrum+ utilized a unique and somewhat complex method for managing screen memory addresses to optimize performance within limited hardware constraints. Unlike linear framebuffers found in modern systems, the Spectrum divided its display into three distinct vertical sections, interleaving memory blocks to allow the ULA to access data efficiently during the television scanout. This article explores the specific memory mapping, the relationship between pixel data and attribute bytes, and the technical reasoning behind this unconventional architecture.

The Memory Map and Base Address

Screen memory on the ZX Spectrum+ begins at decimal address 16384, which corresponds to hexadecimal 0x4000. This region is reserved specifically for the display file, separating it from the BASIC interpreter and user program area. The total space allocated for the display is 6912 bytes. Of this total, 6144 bytes are dedicated to pixel information, while the remaining 768 bytes store color attribute data. This fixed memory map ensured that the video hardware could consistently locate the necessary data without complex dynamic allocation.

Interleaved Screen Layout

The most distinctive feature of the Spectrum’s video memory is its non-linear arrangement. The 256x192 pixel screen is divided into three horizontal thirds, each containing 64 lines of display data. Within memory, these thirds are stored sequentially, but the lines within each third are further interleaved. Each 8-line block is stored together, meaning the first 8 lines of the top third occupy the first block of memory, followed by the next 8 lines, and so on. This organization was designed to match the raster timing of the PAL television signal, allowing the ULA to fetch data in sync with the electron beam scanning the phosphors on the TV screen.

Pixel Data and Attribute Bytes

Pixel data is stored in a monochrome format where each bit represents a pixel, with a value of 1 indicating ink and 0 indicating paper. These bits are grouped into bytes, forming 8x1 pixel blocks. Color information is handled separately through attribute bytes, arranged in a grid of 32 columns by 24 rows. Each attribute byte defines the colors for an 8x8 pixel block, specifying the ink color, paper color, brightness, and flashing status. Because color is applied per 8x8 block rather than per pixel, this architecture leads to the famous attribute clash effect, where multicolored sprites often overwrite each other’s colors within the same character block.

Hardware Contention and Performance

Managing these addresses required careful coordination between the Z80 CPU and the Uncommitted Logic Array (ULA). The ULA accesses screen memory directly to generate the video signal, occasionally halting the CPU to prevent bus conflicts. This phenomenon, known as contentions, occurs primarily during the visible display period. Programmers optimizing for speed had to account for these memory access delays, particularly when updating the screen during the active display time. Understanding the specific address layout allowed developers to write code that minimized visual artifacts and maximized the efficiency of the limited memory bandwidth available.

Conclusion

The screen memory addressing scheme of the Sinclair ZX Spectrum+ remains a fascinating example of engineering compromise. By prioritizing cost-effective hardware design over linear memory simplicity, Sinclair created a system that was affordable yet capable of generating a vibrant display. While the interleaved memory and attribute-based coloring presented challenges for developers, mastering this layout was essential for creating high-performance games and graphics on the iconic home computer.