How the Commodore Amiga 4000 Handles Interrupt Requests

The Commodore Amiga 4000 manages conflicting interrupt requests through a hardware-based priority system coordinated between its AGA chipset and Motorola CPU. This article explores the specific registers involved, the seven-level priority structure, and how the operating system services these signals to ensure stable multitasking and real-time performance. Readers will gain insight into the masking techniques used to prevent data loss during high-load operations.

The AGA Chipset and Interrupt Generation

At the heart of the Amiga 4000 lies the Advanced Graphics Architecture (AGA) chipset, which includes custom chips responsible for generating hardware interrupts. These chips monitor various events such as disk drive activity, audio buffer emptying, and video beam positioning. When an event occurs, the chipset sets a specific bit in the Interrupt Request Register (INTREQ). If the corresponding bit in the Interrupt Enable Register (INTENAR) is active, the signal is passed to the central processor. This hardware-level filtering ensures that only relevant events trigger CPU attention.

CPU Priority Levels and Masking

The Motorola 68040 or 68060 CPU utilized in the Amiga 4000 supports seven interrupt priority levels. Level 0 represents no interrupt mask, while level 7 is reserved for non-maskable interrupts like hardware failures. When multiple interrupts occur simultaneously, the CPU compares the incoming request priority against its current interrupt mask. If the new request has a higher priority than the current mask level, the CPU suspends its current task, saves the context, and jumps to the appropriate interrupt vector. Lower priority requests are held pending until the processor lowers its mask level after servicing the higher priority task.

Resolving Conflicts Through Servicing Order

Conflicting requests are resolved primarily through this strict hierarchy. For example, the vertical blank interrupt, crucial for screen synchronization, typically holds a higher priority than disk block completion. If both signals arrive at the same time, the CPU services the vertical blank first. The interrupt service routines (ISRs) are designed to be reentrant and efficient to minimize latency. Once the high-priority routine completes, the CPU checks the pending register again to service the next highest priority request waiting in the queue.

Operating System Coordination

Kickstart, the Amiga’s built-in operating system firmware, plays a vital role in managing these hardware signals. It provides standard exec libraries that allow software developers to allocate interrupts without causing conflicts. The Exec kernel maintains a list of interrupt servers and ensures that memory is protected during context switches. By coordinating hardware priorities with software resource management, the Amiga 4000 maintains system stability even when multiple peripherals and processes demand immediate processor attention.