How the Commodore Amiga 2000 Handles Interrupts

The Commodore Amiga 2000 manages multiple device interrupts through a centralized hardware system driven by its custom chipset and Motorola 68000 CPU. This article details the role of the Agnus chip in coordinating signals, the function of interrupt enable and request registers, and how expansion devices utilize the Zorro II bus to communicate with the processor without causing system conflicts.

Centralized Interrupt Control

At the heart of the Amiga 2000 interrupt system is the Agnus chip, which acts as the primary arbiter for direct memory access and interrupt signals. Various subsystems, including the disk drive, serial port, and audio channels, send interrupt signals to Agnus rather than directly to the CPU. This design prevents the Motorola 68000 processor from being overwhelmed by simultaneous hardware requests and ensures a standardized pathway for signal management.

Interrupt Registers and Masking

Software control over interrupts is managed through two specific memory-mapped registers: INTREQ and INTENA. The INTREQ register reflects the current state of hardware interrupt requests, allowing the CPU to identify which device requires attention. The INTENA register allows the operating system or application to mask specific interrupt sources, enabling or disabling them individually to prioritize critical tasks during high-load operations.

Zorro II Expansion Slot Interrupts

Unlike the compact Amiga 500, the Amiga 2000 features Zorro II expansion slots that allow third-party hardware to generate interrupts. Expansion cards utilize the autoconfig protocol to claim interrupt vectors during system startup. These devices signal requests through the backplane, which routes them to the main interrupt controller, ensuring that add-on hardware integrates seamlessly with the existing interrupt hierarchy without manual configuration.

CPU Servicing and Prioritization

When the Agnus chip asserts the IRQ line, the Motorola 68000 CPU halts its current task and jumps to the appropriate interrupt vector table. The system employs a fixed hardware priority scheme where certain events, such as the vertical blank interrupt, take precedence over others like serial port reception. Once the source is identified via the INTREQ register, the CPU executes the specific interrupt service routine before returning to the previous workflow, maintaining system stability across multiple concurrent devices.