How Many Interrupt Lines on Sinclair ZX Spectrum+

This article provides a technical overview of the interrupt capabilities within the Sinclair ZX Spectrum+ architecture, specifically addressing hardware accessibility for developers. It clarifies the distinction between internal CPU interrupts and external expansion possibilities, ultimately revealing that there was exactly one interrupt line available for user programming via the expansion port.

The Sinclair ZX Spectrum+ shares the same core hardware architecture as the original 48K ZX Spectrum, utilizing the Zilog Z80A microprocessor. Understanding the interrupt system requires knowledge of the Z80 CPU, which supports two primary hardware interrupt inputs: the maskable interrupt (INT) and the non-maskable interrupt (NMI). In the standard configuration of the Spectrum+, the maskable interrupt is generated internally by the Uncommitted Logic Array (ULA) to synchronize with the video refresh rate, typically occurring 50 times per second in PAL regions. This internal INT line is not exposed for external triggering by the user.

For hardware enthusiasts and programmers looking to interface external devices, the critical factor is the expansion port located on the rear of the machine. The pinout of this edge connector exposes specific CPU control signals. Among these signals, the Non-Maskable Interrupt line, denoted as /NMI, is made available to the user. This allows external hardware to force the CPU to execute a specific routine regardless of the current state of the interrupt flip-flop, making it a powerful tool for real-time hardware interfacing.

Consequently, while the Z80 CPU theoretically supports multiple interrupt modes, the physical design of the Sinclair ZX Spectrum+ limits external user access to a single line. The /INT line remains under the control of the ULA for video timing, leaving the /NMI line as the sole interrupt input accessible for user programming through the expansion connector. This single line enabled the creation of various hardware add-ons, such as disk interfaces and custom I/O controllers, that required immediate CPU attention without relying on software polling loops.

In summary, the hardware design prioritizes video stability over external interrupt flexibility. By restricting user access to the maskable interrupt, Sinclair ensured that the display generation remained consistent. Therefore, developers working with the ZX Spectrum+ had exactly one interrupt line available for user programming, relying on the NMI signal for high-priority external hardware events.