How Many Interrupt Levels Does Amiga 4000 Support

The Commodore Amiga 4000 hardware supports a total of eight interrupt levels, numbered from 0 to 7. This capability is derived from the Motorola 68040 central processing unit that powers the system, which adheres to the standard interrupt architecture of the 68k family. Understanding these levels is essential for low-level programming and hardware expansion, as they determine how the processor prioritizes and masks asynchronous events during operation.

These eight levels are managed through three interrupt mask bits located within the CPU status register. These bits allow the processor to ignore interrupts of a lower priority while it is busy servicing a higher priority request. Level 0 indicates that no interrupts are masked, allowing all hardware requests to be processed immediately. At the other end of the spectrum, level 7 is reserved for non-maskable interrupts, ensuring that critical system events such as reset conditions are always handled regardless of the current processor state.

While the CPU supports eight levels, the Amiga custom chipset typically routes its hardware interrupt requests to the processor at level 2. The custom chips, including Agnus and Denise, utilize an internal priority encoder to manage multiple sources like vertical blanking, disk drives, and audio before signaling the CPU. The Exec operating system then manages these requests through a linked list of interrupt servers, leveraging the underlying eight-level hardware structure to maintain system stability and multitasking performance.