How Does the Commodore 128 Handle Interrupt Requests?

The Commodore 128 manages interrupt requests through a complex interplay between its 8502 microprocessor, CIA I/O chips, and video controllers. This article explores the hardware architecture behind IRQs, details the specific memory vectors used for processing, and explains the differences between interrupt handling in C64 compatibility mode versus native 128 mode. Understanding these mechanisms is essential for developers creating low-level software or hardware expansions for the platform.

Hardware Architecture and IRQ Sources

At the heart of the Commodore 128 interrupt system is the 8502 CPU, which features a single IRQ input line. Multiple hardware components compete for attention on this line, requiring the system to identify the source once an interrupt is triggered. The primary sources include the 8521 Complex Interface Adapter (CIA) located at I/O port 1, the 8520 CIA at I/O port 2, and the video chips. In 40-column mode, the VIC-IIe generates raster interrupts, while in 80-column native mode, the 8563 VDC provides its own interrupt signals. The CIA chips typically handle system timing, keyboard scanning, and user-defined timers, making CIA1 Timer A the most common source for the standard system tick.

Memory Vectors and Processing Flow

When the 8502 CPU receives an interrupt signal, it completes the current instruction and pushes the processor status and program counter onto the stack. It then jumps to a specific memory address known as the IRQ vector. On the Commodore 128, the standard IRQ vector is located at addresses $0314 and $0315. By default, these addresses point to the Kernal ROM routine responsible for servicing standard system tasks. This routine checks the interrupt status registers of the CIA and video chips to determine the cause of the interrupt. If the interrupt is recognized as a system timer tick, the Kernal updates the system clock and checks for keyboard input before returning control to the main program via an RTI instruction.

Differences Between Operating Modes

Interrupt handling varies significantly depending on whether the machine is operating in C64 mode or Native mode. In C64 mode, the architecture mimics the Commodore 64, utilizing the VIC-IIe chip for video interrupts and relying heavily on CIA1 for system timing. The memory map and Kernal routines are structured to maintain compatibility with existing C64 software. Conversely, Native mode utilizes the 8563 VDC for 80-column display, which has different interrupt capabilities and registers. Developers writing native software must account for the different vector locations and hardware registers associated with the VDC, although the standard IRQ vector at $0314 often remains the entry point for custom handlers that chain back to the Kernal.

Implementing Custom Interrupt Handlers

Advanced programmers often replace the default IRQ vector with custom routines to achieve precise timing or game logic independent of the system clock. To do this, the address of the custom routine is stored in $0314 and $0315. A well-behaved custom handler usually processes the specific hardware interrupt it is designed for and then jumps to the original Kernal IRQ routine to ensure system stability is maintained. Failure to service the CIA interrupt flags properly can result in the IRQ line remaining active, causing the CPU to enter an interrupt loop that freezes the system. Proper management of the interrupt mask registers in the CIA chips is therefore critical when modifying the default interrupt behavior.