How Did the Commodore Plus/4 Handle Hardware Scrolling?

The Commodore Plus/4 utilized its integrated TED chip to manage display output, offering specific hardware registers for screen manipulation. This article explores the technical mechanics behind the Plus/4’s scrolling capabilities, detailing the specific memory addresses used for fine adjustment and explaining how the system differed from its predecessor, the Commodore 64. Readers will gain insight into the horizontal and vertical scroll registers, the impact of CPU cycle stealing on performance, and the practical limitations developers faced when implementing smooth motion in games.

The TED Chip Architecture

At the heart of the Commodore Plus/4, Commodore 16, and Commodore 116 computers was the TED (Text Editing Device) chip, officially known as the 7360. Unlike the VIC-II chip found in the Commodore 64, which separated video processing from the main system logic, the TED chip integrated video generation, DRAM refresh, and interrupt control into a single unit. This integration allowed for a lower cost of production but introduced specific constraints regarding how the screen buffer was accessed and manipulated. The video matrix and character sets were stored in main RAM, and the TED chip accessed this memory directly to generate the video signal, competing with the 7501 CPU for memory bandwidth.

Horizontal and Vertical Scroll Registers

Hardware scrolling on the Plus/4 was achieved through specific bits within the TED control registers. To perform fine scrolling, developers utilized three bits in two separate registers to shift the display by individual pixels. Register $D011 (Control Register 1) contained the vertical scroll bits in positions 0 through 2, allowing for a vertical shift of 0 to 7 pixels. Similarly, register $D016 (Control Register 2) housed the horizontal scroll bits in positions 0 through 2, enabling a horizontal shift of 0 to 7 pixels. By adjusting these values, the hardware could offset the start of the video fetch without requiring the CPU to move the entire screen matrix in memory, providing a smooth visual transition.

Limitations and Cycle Stealing

While the TED chip provided hardware registers for fine scrolling, the implementation was often more challenging than on competing systems due to memory bandwidth issues. The TED architecture employed a technique known as cycle stealing, where the video circuitry paused the CPU to fetch video data from RAM. During standard text or graphics modes, this could consume a significant portion of the CPU’s available cycles. When developers attempted to update scroll registers frequently to create smooth motion, the reduced CPU availability often led to performance bottlenecks. Consequently, many games on the Plus/4 relied on coarse scrolling, where the screen matrix was shifted by whole character blocks, rather than utilizing the fine scrolling registers for every frame.

Comparison to the VIC-II

The scrolling mechanism on the Plus/4 is frequently compared to the VIC-II chip in the Commodore 64, which is renowned for its smooth scrolling capabilities. While both chips used 3-bit registers for fine scrolling, the VIC-II benefited from a more robust memory arbitration system that allowed for smoother gameplay during intense scrolling sequences. The TED chip’s tighter integration meant that enabling certain video features or high-resolution modes could further restrict CPU access. As a result, while the Plus/4 was capable of hardware scrolling, the technical overhead required to maintain a stable frame rate while scrolling often led developers to optimize for static screens or limited movement areas.

Conclusion

The Commodore Plus/4 handled screen scrolling through dedicated bits in the TED chip’s control registers, allowing for fine adjustment of the display position. Although the hardware supported pixel-level scrolling via registers $D011 and $D016, the system’s memory bandwidth limitations and cycle stealing mechanisms posed significant challenges for developers. These constraints defined the visual style of Plus/4 software, distinguishing its performance characteristics from other 8-bit contemporaries and highlighting the trade-offs made in the computer’s integrated design.