Amiga 500 CPU and Custom Chip Memory Mapping Explained

The Commodore Amiga 500 utilizes a unique shared memory architecture where the central processor and custom graphics and sound chips access the same physical RAM. This article explores the role of the Agnus chip in arbitrating bus access, the distinction between Chip RAM and Fast RAM, and the cycle-stealing mechanism that ensures smooth multimedia performance without dedicated video memory.

The Unified Memory Architecture

Unlike modern computers that often separate system memory from video RAM, the Amiga 500 employs a unified memory pool. The Motorola 68000 CPU and the Original Chip Set (OCS), consisting of Agnus, Denise, and Paula, all read and write to the same memory modules. This design was cost-effective and allowed for flexible data sharing, such as using CPU-calculated data directly for graphics or sound without complex copying procedures. However, sharing a single bus requires strict management to prevent data collisions.

The Role of the Agnus Chip

At the heart of the memory management system is the Agnus chip. While the CPU executes instructions, Agnus acts as the gatekeeper for all memory access. It contains the Address Generator and the DMA (Direct Memory Access) controller. Every request for memory access, whether from the CPU or the custom chips, must pass through Agnus. It determines who gets access to the bus and when, ensuring that critical real-time operations for graphics and audio take precedence over general CPU processing when necessary.

Bus Arbitration and Cycle Stealing

The Amiga 500 memory bus operates on a cycle basis. In a standard low-resolution scenario, the system alternates access between the CPU and the custom chips. The CPU typically accesses memory on even cycles, while the custom chips access memory on odd cycles. This allows both to run at full speed without interference. However, during high-bandwidth situations, such as displaying high-resolution graphics or playing multiple audio channels, the custom chips require more bandwidth.

When the custom chips need more access than the odd cycles provide, Agnus employs a technique known as cycle stealing. It halts the CPU for specific cycles to grant the custom chips immediate access to the memory bus. While this ensures glitch-free audio and video, it reduces the effective processing power available to the CPU. This dynamic arbitration is why the Amiga could maintain smooth graphics even while the CPU was under heavy load, though complex calculations could slow down during intense display periods.

Chip RAM vs. Fast RAM

The memory accessible by both the CPU and the custom chips is known as Chip RAM. On the standard Amiga 500, this is typically 512KB, though it can be expanded to 1MB. Because the custom chips must access this memory for display lists and audio samples, it is subject to the contention and cycle stealing described above.

Expansions for the Amiga 500 often introduced Fast RAM. This memory is connected directly to the CPU bus and is invisible to the custom chips. When the CPU accesses Fast RAM, it does not need to arbitrate with Agnus, allowing it to run at full speed without cycle stealing. This distinction is crucial for software optimization; code and data that do not require custom chip access are best placed in Fast RAM to maximize system performance.

Direct Memory Access Channels

The custom chips utilize DMA channels to manage data transfer without CPU intervention. Paula handles audio DMA, fetching sample data directly from memory to the audio buffers. Agnus manages the graphics DMA, fetching sprite data, bitplane information, and copper instructions. Because these transfers happen directly between memory and the chips via the arbitration logic, the CPU is free to perform other tasks. This efficient memory mapping strategy was a key factor in the Amiga 500’s reputation for superior multimedia capabilities during the 16-bit era.